DIFFERENTIAL OSCILLATOR
YN6312M500332015P 2.0 × 1.6 mm LVPECL differential crystal oscillator at 312.500 MHz.

YN6312M500332015P 2.0 × 1.6 mm Differential Crystal Oscillator
YN6312M500332015P is a 2.0 × 1.6 mm DYN Series LVPECL differential crystal oscillator specified for 312.500 MHz operation at 3.3 V, with ±20 ppm frequency stability and 35 fs typical RMS phase jitter.
Quick Product Answers
What is YN6312M500332015P?
YN6312M500332015P is a 2.0 × 1.6 mm DYN Series LVPECL differential crystal oscillator specified for 312.500 MHz operation at 3.3 V, with ±20 ppm frequency stability and 35 fs typical RMS phase jitter.
What are the key specifications of YN6312M500332015P?
Package size: 2.0 × 1.6 mm; Frequency range: 312.500 MHz; Operating temperature range: -40 °C to +105 °C; Frequency stability: ±20 ppm; Supply voltage: 3.3 V.
What applications is YN6312M500332015P intended for?
Use the documented applications and electrical requirements on this page to confirm suitability for the intended design.
How should engineers select YN6312M500332015P?
Select YN6312M500332015P only when its documented frequency, package size, operating-temperature range and tolerance or stability match the design. Where applicable, also verify load capacitance, supply voltage and output waveform in the datasheet.
- Model
- YN6312M500332015P
- Package size
- 2.0 × 1.6 mm
- Frequency
- 312.500 MHz
- Output type
- LVPECL
- Frequency stability
- ±20 ppm
- Operating temperature
- -40 °C to +105 °C
Product Features
Technical Specifications
| Model | YN6312M500332015P |
|---|---|
| Package size | 2.0 × 1.6 mm |
| Output type | LVPECL |
| Supply voltage | 3.3 V |
| Frequency range | 312.500 MHz |
| Oscillation mode | Fundamental |
| Frequency stability | ±20 ppm |
| Frequency stability conditions | Includes initial frequency tolerance, temperature variation, supply voltage change and 10 years aging (+25 °C) |
| Operating temperature range | -40 °C to +105 °C |
| Storage temperature range | -55 °C to +125 °C |
| High-level output voltage | VDD - 1.1 V min. |
| Low-level output voltage | VDD - 1.5 V max. |
| Current consumption | 60 mA max.; RL = 50 Ω to VDD - 2 V |
| Rise time | 0.4 ns |
| Fall time | 0.4 ns |
| Rise/fall measurement | Between 20% and 80% of (VOH - VOL) |
| Symmetry | 45% to 55% |
| Differential swing | 0.8 V to 2.0 V |
| Start-up time | 10 ms; t = 0 at 90% VCC |
| Output load | 50 Ω; terminated to VCC - 2.0 V |
| Tri-State - Output Enable | 70% VDD min. |
| Tri-State - Output Disable | 30% VDD max. |
| Tri-State conditions | Output enabled if OE is Logic 1 or open; disabled if OE is Logic 0 |
| RMS phase jitter | 35 fs typ.; integrated from 12 kHz to 20 MHz at 312.5 MHz, 3.3 V |
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